Description
Chip and FPGA design needs heavy simulation, commercial licenses are steep and open tools are slow. Verilator is an open-source SystemVerilog simulator and lint system.
It compiles Verilog into optimized C++ models, rivaling commercial speeds with multithreading.
Compiled:To C++.
Fast:Multithreaded.
Lint:Checks.
Free:No licenses.
It compiles Verilog into optimized C++ models, rivaling commercial speeds with multithreading.
Features
Compiled:To C++.
Fast:Multithreaded.
Lint:Checks.
Free:No licenses.
