Description
FPGA or chip design means installing separate open tools for synthesis, simulation, place-and-route and formal verification, with version headaches. OSS CAD Suite packages Yosys, nextpnr, Verilator and other open source digital design and verification tools as multi-platform nightly builds.
Download and unzip on Linux, macOS or Windows with matching tool versions.
Full suite:Synthesis to verification.
Nightly:Always current.
Platforms:All three.
No install:Unzip and go.
Download and unzip on Linux, macOS or Windows with matching tool versions.
Features
Full suite:Synthesis to verification.
Nightly:Always current.
Platforms:All three.
No install:Unzip and go.
