Description
Chip layout work means juggling GDS2, LEF, DEF and OASIS, commercial EDA licenses cost a fortune, and multi-gigabyte layouts crawl. Glade is a free IC layout, schematic and netlist editor, named after the GDS, LEF and DEF formats it speaks.
It opens large design databases smoothly, includes DRC, LVS and parasitic extraction, scripts in Python, and runs on Windows, Linux and macOS.
Formats:Read and write GDS2, OASIS, LEF/DEF and Verilog netlists.
Large layouts:Pan and zoom multi-gigabyte databases quickly.
DRC and LVS:Built-in design rule and layout-versus-schematic checks.
Python:Script repetitive layout tasks.
It opens large design databases smoothly, includes DRC, LVS and parasitic extraction, scripts in Python, and runs on Windows, Linux and macOS.
Features
Formats:Read and write GDS2, OASIS, LEF/DEF and Verilog netlists.
Large layouts:Pan and zoom multi-gigabyte databases quickly.
DRC and LVS:Built-in design rule and layout-versus-schematic checks.
Python:Script repetitive layout tasks.
